 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| KM68512B Family Document Title 64Kx8 bit Low Power CMOS Static RAM Advance CMOS SRAM Revision History Revision No. 0.0 History Initial draft Draft Data January 10th 1998 Remark Advance The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you ha ve any questions, please contact the SAMSUNG branch office near you. 1 Revision 0.0 January 1998 KM68512B Family 64Kx8 bit Low Power CMOS Static RAM FEATURES * * * * * * Process Technology : 0.4 m CMOS Organization : 64Kx8 Power Supply Voltage : Single 5V 10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 32-TSOP I -0820F Advance CMOS SRAM GENERAL DESCRIPTION The KM68512B family is fabricated by SAMSUNG s advanced CMOS process technology. The family support various operating temperature ranges and small package type for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM68512BL-L KM68512BLI-L Operating Temperature Commercial(0~70 C) Industrial(-40~85 C) VCC Range Speed(ns) 55/70 70 Standby (ISB1, Max) 10A 15A Operating (ICC2, Max) 60mA PKG Type 5V0.5V 32-TSOP1-F PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A4 A5 A6 A7 A8 A12 A13 A14 A15 32-TSOP Type1 - Forward Row select Memory array 512 rows 128x8 columns Name A0~A15 WE CS1, CS2 OE I/O1~I/O8 Vcc Vss N.C Function Address Inputs Write Enable Input Chip Select Inputs Output Enable Input Data Inputs/Outputs Power I/O1 I/O8 Data cont I/O Circuit Column select Data cont A0 A1 A2 A3 A9 A10 A11 CS Ground No Connection CS2 WE OE Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 0.0 January 1998 KM68512B Family PRODUCT LIST Commercial Temperature Product (0~70C) Part Name KM68512BLT-5L KM68512BLT-7L Function 32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr Advance CMOS SRAM Industrial Temperature Products (-40~85C) Part Name KM68512BLTI-7L Function 32-TSOP1-F, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X 1) OE X 1) WE X 1) I/O Pin High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active L H H H X1) H L X X1) H H L 1. X means dont care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time 1) Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 260C, 10sec(Lead Only) Unit V V W C C C - Remark KM68512BL KM68512BLI - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect r eliability. 3 Revision 0.0 January 1998 KM68512B Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.5 3) Advance CMOS SRAM 1) Typ 5.0 0 - Max 5.5 0 Vcc+0.5V 2) 0.8 Unit V V V V Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot is sampled, not 100% tested CAPACITANCE 1)(f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 6 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) 1. Industrial product = 15A Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read Cycle time=1 A , 100% duty, IIO=0mA CS10.2V, CS2VCC-0.2V, VIN0.2V or VINVcc -0.2V Read Write Min -1 -1 2.4 - Typ Max Unit 7 1 1 1 10 5 30 60 0.4 3 101) A A mA mA mA mA V V mA A Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH VOL VOH ISB ISB1 IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs =VIL or VIH CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V 4 Revision 0.0 January 1998 KM68512B Family AC OPERATING CONDITIONS TEST CONDITIONS ( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and faling time : 5ns Input and output reference voltage :1.5V Output load(see right) : C L=100pF+1TTL Advance CMOS SRAM CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512B Family : TA=0 to 70C, KM68512BI Family : TA=-40 to 85C) Speed Bins Parameter List Symbol Min 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 55 0 0 30 0 5 70ns Max 70 70 35 25 25 25 - Units Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP 55 10 5 0 0 10 55 45 0 45 40 0 0 20 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tWR tWHZ tDW tDH tOW DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR 1) Test Condition CS1 Vcc-0.2V Vcc=3.0V, CS1Vcc-0.2V KM68512BL-L KM68512BLI-L See data retention waveform Min 2.0 0 5 Typ 0.5 - Max 5.5 10 15 - Unit V A ms 1. CS1Vcc-0.2V, CS2Vcc-0.2V( CS1 controlled) or CS20.2V(CS2 controlled). 5 Revision 0.0 January 1998 KM68512B Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address tOH Data Out Previous Data Valid tAA (Address Controlled, CS=OE=VIL, WE=VIH) Advance CMOS SRAM tRC Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ tOHZ Data out NOTES (READ CYCLE) High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 0.0 January 1998 KM68512B Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) Advance CMOS SRAM tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out tDW tDH tWR(4) Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in tDH tCW(2) tWR(4) Data Valid Data out High-Z High-Z 7 Revision 0.0 January 1998 KM68512B Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled) Advance CMOS SRAM tWC Address tAS(3) CS1 tAW CS2 tWP(2) tWP(1) tDW Data in tDH tCW(2) tWR(4) WE Data Valid Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CSVCC - 0.2V CS1 GND CS2 controlled VCC 4.5V* CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS20.2V 8 Revision 0.0 January 1998 KM68512B Family PACKAGE DIMENSIONS 32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F) 0.20 +0.10 -0.05 0.008+0.004 -0.002 Advance CMOS SRAM Units : Millimeters(Inches) 20.000.20 0.7870.008 #32 ( 8.00 0.315 0.25 ) 0.010 #1 MAX 8.40 0.331 0.50 0.0197 #16 #17 1.000.10 0.0390.004 1.20 0.047 MAX 0.05 0.002 MIN 0.25 0.010 TYP 18.400.10 0.7240.004 0.10 MAX 0.004 MAX +0.10 -0.05 0.006+0.004 -0.002 0.15 0~8 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 9 Revision 0.0 January 1998 |
Price & Availability of KM68512BLI-L
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |